GPIO Principles#
GPIO provides 54 interfaces through MIO, with 16 located in bank 500 and the remaining in bank 501. It also provides 64 inputs and 128 outputs from PL through the EMIO interface. The memory mapping for GPIO control and status registers is at base address $0xE000_A000$.
The GPIO pins of ZYNQ are divided into 4 banks, totaling 118 GPIOs.
Internal Structure of GPIO#
From the figure, we can see that GPIO has three functions: input, output, and interrupt.
MIO 7 and 9 can only be used for output.
A set of registers can control all pins of a single GPIO bank.
GPIO Control of Device Pins#
Input/Output Registers#
| Register Name | Description |
|---|---|
| DATA_RO | The value of the GPIO pins is stored in this register, and the value can be read regardless of whether the GPIO is configured as input or output. Since it is a read-only register (for software), write operations to this register will be ignored. |
| DATA | Output data register, effective only when the GPIO is configured as output; the value in this register is the value output to the pins. Writing to this register sets the output value of the GPIO, reading this register will return the previous output value of the GPIO, not the current value. |
| MASK_DATA_LSW | Mask Data Least Significant Words, output data low 16 bits mask register; only the low 16 bits are valid, corresponding bits set to 1 indicate that the corresponding bits in the DATA register's low 16 bits can be changed, if not 1, it means the corresponding bits in the DATA register's low 16 bits retain their original value. |
| MASK_DATA_MSW | Mask Data Most Significant Words, output data high 16 bits mask register, functions the same as MASK_DATA_LSW, but it corresponds to the high 16 bits of the DATA register. |
| DIRM | Direction Memory, direction register; defaults to 0 for input, set to 1 for output. Note that even if DIRM is 1, software can still read the level of this pin as if it were an input. |
| OEN | Output Enable, output enable register; valid only when DIRM is 0, set to 1 for output enabled, set to 0 for output disabled, at which point the value on the corresponding pin is a tri-state value. |
Interrupt Control Registers#
| Register Name | Description |
|---|---|
| INT_TYPE | Interrupt Type register, controls whether GPIO interrupts are level-triggered or edge-triggered. |
| INT_POLARITY | Interrupt Polarity register controls whether GPIO interrupts are valid on low level/falling edge or high level/rising edge. |
| INT_ANY | Interrupt Any, dual-edge register; this register is valid only when INT_TYPE is edge-triggered, controlling whether interrupts can be triggered on both edges. |
| INT_STAT | Interrupt State register; the value of this register will be read by the connected INT State D flip-flop. The D flip-flop stores the interrupt state, and software can determine if an interrupt has occurred by reading the output of this D flip-flop. Clearing this D flip-flop clears the interrupt state. |
| INT_MASK | Interrupt Mask register; shows which bits are currently masked and which are enabled. |
| INT_DIS | Interrupt Disable register; writing 1 to any bit of this register will mask that interrupt signal. reading from this register will return an unpredictable value. |
| INT_EN | Interrupt Enable register; writing 1 to any bit of this register can enable/disable the interrupt signal mask. reading from this register will return an unpredictable value. |
The interrupt number for GPIO is ==52==, and the interrupt priority is fixed, so there is no need to configure the interrupt priority for GPIO. All GPIO pins share the same interrupt; even if interrupts for two pins are enabled, the software cannot determine which pin the interrupt came from.
EMIO and MIO#
MIO, Multiuse I/O, multiplexed input/output, corresponds to the configurable multifunction pins on the PS side.
EMIO, Extended MIO, corresponds to the configurable multifunction pins on the PL side.
MIO is the basic pin for peripherals; due to the limited number of MIO pins, ZYNQ also provides the EMIO interface as an extension of MIO, allowing peripherals to connect to the pins on the PL side through the EMIO interface to achieve almost the same functionality as MIO.
The differences between MIO and EMIO are as follows:
- MIO is transparent to the PL side; the PL cannot read the levels on the MIO pins; the PS side can communicate with the PL side through EMIO.
- Peripherals are fixedly paired with MIO, and pin constraints must be selected based on the development board schematic during initialization. EMIO is relatively flexible; pins can be arbitrarily specified and constrained to a specific pin on the PL side through the xdc file.
- Because MIO pins are closer to peripheral circuits, some peripherals perform better using MIO compared to EMIO, and some peripherals can only use MIO.
Differences and Connections Between MIO Bank and Package Bank#
MIO is divided into Bank 0 and Bank 1; Bank 0 contains part of the pins in package Bank 500, and Bank 1 contains part of the pins in package Bank 501.
Bank 0 includes MIO 0~15, totaling 16 MIOs, while bank 1 includes MIO 16~53, totaling 38 MIOs, for a total of 54 MIOs. EMIO has a total of 64.
