In large FPGA designs, synchronous sequential circuits are recommended. Synchronous sequential circuits are designed based on clock trigger edges and have higher requirements for clock period, duty cycle, delay, and jitter. To meet timing requirements, a global clock resource is generally used to drive the main clock. The main clock in an FPGA is typically implemented using a full copper layer process and designed with dedicated clock buffering and driving structures.
1 Buffering and Driving#
1.1 Buffering#
Input/output buffering is mainly used for external input clocks or external differential input signals.
Differential signals and differential clocks cannot be processed directly after entering the chip without going through IBUFGDS or IBUFDS buffering.
1.2 Driving#
When the signal fanout is too large, adding a BUFG can increase signal stability.
There is about a 10ns delay through a BUFG, but the delay to all cells on the chip after passing through the BUFG can be ignored.
2 Types and Functions of Buffers#
2.1 BUFG#
BUFG is a high-fanout buffer that connects signals to global routing resources, minimizing signal delay and jitter.
It is typically used in clock networks and other high-fanout networks, such as reset and enable signals.
2.2 BUFGCE#
BUFGCE is a global clock buffer with a single gate-controlled input, where CE is active high.
When CE is low, the O port outputs 0.
2.3 BUFH#
The BUFH primitive allows direct access to the clock region entry of BUFG, enabling access to unused parts of the global clock network as a high-speed, low-offset local routing resource (single clock region).
2.4 IBUFDS#
A buffer that supports low-voltage differential signal input, with two input ports, one for the main port and one for the secondary port, where the input signal phases are opposite.
2.5 IBUFDS_GTE2#
Gbit transceiver input buffer in 7 series devices, REFCLK should be connected to the dedicated reference clock input pin of the serial transceiver.
2.6 OBUFDS#
Differential signal output buffer.