ERROR: [Common 17-49] Internal Data Exception:#
This error usually indicates a problem when using vvdo for logic analysis. The error message suggests that there is an assertion failure, meaning that the data does not match when retrieving probe data.
Synth 8-5535#
Error code
[Synth 8-5535] port <clk_0> has illegal connections. It is illegal to have a port connected to an input buffer and other components. The following are the port connections :
Input Buffer:
Port I of instance clkin1_ibufg(IBUF) in module <top_clk_wiz_0_1_clk_wiz>
Other Components:
Cause#
The clock signal of a general IO input must go through a buffer to drive the PLL.
Solution#
Configure the input signal in the clocking wizard to No Buffer.
Warning: filegmt 56-199#
Solution#
Right-click in the Sources panel and select refresh hierarchy.
Warning: CRITICAL WARNING: [filemgmt 56-176] Module references are not supported in manual compile order mode and will be ignored.#
Solution#
Set the refresh hierarchy mode to automatic update and compile.
[BD 41-237] Bus Interface property FREQ_HZ does not match between /M_AXIS_DATA_0(100000000) and /dds_compiler_0/M_AXIS_DATA(200000000)#
The cause of this error is that the clock frequency of the IP core is 200M, while the frequency of the AXI4s port is 100M. Therefore, set the port frequency to match the frequency of the IP core.
Various settings in Vivado cannot be saved.#
Cause#
The file "C:\Users\31651\AppData\Roaming\Xilinx\Vivado\2023.2\vivado.xml" stores Vivado settings, such as recently opened files.
If there are Chinese characters or other characters that Vivado cannot recognize in these paths, Vivado will not be able to read these configurations properly each time it starts, resetting this file, resulting in the loss of all configurations after restarting Vivado.
Solution#
Remove or rename file paths containing Chinese characters to English.
[Common 17-180] Spawn failed: No error#
Cause#
In Vivado, the error message "[Common 17-180] Spawn failed: No error" indicates that Vivado was unable to successfully start or create a certain process, despite the lack of a specific error message. This error typically occurs when Vivado attempts to start an external process or perform certain operations, such as compiling, generating bitstreams, or launching simulation tools.
TIMING #1 Critical Warning A primary clock top_i/clk_wiz_0/inst/clk_in 1 is created on an inappropriate pin top_i/clk_wiz_0/inst/clk_in 1. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc)#
When outputting a 120 MHz clock from PS, the actual output frequency is $125MHz$, so a clk_wiz is cascaded after the PS clock output to convert the clock frequency. The error occurs after synthesis.
Solution#
Since a buffer was added to the clk-wiz input, the warning can be resolved by simply setting the input to no buffer.