Sawen_Blog

0.1.1 1. Synthesis Strategy#

• Function: Controls the optimization direction of the synthesis tool (performance, area, power consumption).
• Options:
  • Vivado Synthesis Defaults: Default strategy, balancing performance and resources.
  • AreaOptimized_high: Prioritizes reducing resource usage (e.g., LUTs, registers).
  • PerformanceOptimized_high: Prioritizes timing performance (reducing critical path delay).
  • PowerOptimized_high: Optimizes power consumption (requires power constraints).
• Configuration Location:
  • Vivado's Project Settings > Synthesis > Strategy.
  • Command line: set_property strategy <strategy_name> [current_run]

0.1.2 2. Key Optimization Attributes#

0.1.2.1 (1) Resource Control#

• MAX_FANOUT:
  • Limits the maximum fanout of signals to reduce timing issues caused by high fanout networks.
  • Setting method: Add set_property MAX_FANOUT <value> [get_nets <net_name>] in RTL code or XDC constraints.
• RAM_STYLE:
  • Specifies the RAM implementation method (block uses BRAM, distributed uses LUTRAM).
  • Example: set_property RAM_STYLE block [get_cells <ram_instance>].
• USE_DSP48:
  • Forces multipliers to use DSP48 units (instead of LUTs) to enhance performance.
  • Setting method: set_property USE_DSP48 yes [get_cells <mult_instance>].

0.1.2.2 (2) Timing Optimization#

• Retiming:
  • Adjusts logic positions across registers to balance critical path delay.
  • Enable method: Check Perform register retiming in synthesis settings.
• Control Set Optimization:
  • Merges registers with the same control signals (reset/enables) to reduce the number of control sets.
  • Options: Auto (default) or Aggressive.

0.1.3 3. Cross-Clock Domain (CDC) Handling#

• Asynchronous Path Constraints:

  • Set set_false_path or set_clock_groups for cross-clock domain paths to avoid invalid timing analysis.

  • Example:

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    set_clock_groups -asynchronous -group {clkA} -group {clkB}
    

• Synchronizer Recognition:
  • Vivado automatically recognizes common synchronizer structures (e.g., dual registers) without additional constraints.

0.1.4 4. Incremental Synthesis#

• Function: Only re-synthesize modified parts to shorten compilation time.
• Enable Conditions:
  • A checkpoint file (.dcp) must be generated after the first synthesis.
  • Check the Incremental Synthesis option during subsequent runs.
• Applicable Scenarios: Small design iterations to avoid lengthy full processes.

0.1.5 5. Key Settings in Constraint Files (XDC)#

• Clock Definition:

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  create_clock -period 10 [get_ports clk]  ; Define a 10ns period clock
  

• Input/Output Delays:

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  set_input_delay 2.0 -clock [get_clocks clk] [get_ports data_in]
  set_output_delay 1.5 -clock [get_clocks clk] [get_ports data_out]
  

• Multi-Cycle Paths:

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  set_multicycle_path 2 -setup -from [get_pins {regA|C}] -to [get_pins {regB|D}]
  

0.1.6 6. Synthesis Report Analysis#

Command to generate report: report_timing_summary -file timing.rpt
Key metrics:

• WNS (Worst Negative Slack): Worst negative slack (should be ≥0).
• Resource Utilization: Proportion of LUTs, FFs, BRAMs, DSPs used.
• Clock Frequency: Check if the target frequency is met (Target Frequency).

0.1.7 7. Common Issues and Tuning#

• High Fanout Networks:
  • Solution: Insert BUFG (global buffer) or duplicate registers.
• Critical Path Not Optimized:
  • Check logic hierarchy and manually add pipelines (pipeline).
• Too Many Control Sets:
  • Reduce the variety of reset/enable signals or enable Control Set Optimization.

0.1.8 Summary#

The core of Vivado synthesis settings is to collaboratively optimize design goals (performance/area/power) through strategies, attributes, and constraints. Recommendations:

1. Initial Stage: Use the default strategy and gradually add constraints.
2. Timing Violations: Prioritize adjusting PerformanceOptimized_high and Retiming.
3. Resource Constraints: Enable AreaOptimized_high and resource sharing (e.g., Resource Sharing).
4. Iterative Optimization: Combine synthesis reports with incremental compilation for quick verification of modifications.