1. Synthesis Options#
-
Optimization Level (
-O
or--optimize
)0
: Default optimization, reduces compilation time.1
: Reduces power consumption (runsPower_DefaultOpt
strategy).2
: Increases kernel speed (addsPHYS_OPT_DESIGN
step).3
: Maximum performance (enables retiming and physical optimization).s
: Reduces logic resources (runsArea_Explore
strategy).quick
: Shortens implementation time (enablesFlow_RuntimeOptimized
).
-
Synthesis Strategy (
vivado.synth_strategy
)- Includes default strategy (
Synthesis_Defaults
), quick runtime optimization (Flow_RuntimeOptimized
), and custom strategies.
- Includes default strategy (
-
RTL Language Selection (
vivado.rtl
)- Specify as
verilog
orvhdl
.
- Specify as
-
Hierarchy Management (
-flatten_hierarchy
)- Options:
none
(maintain hierarchy),full
(fully flatten),rebuilt
(rebuild hierarchy afterwards).
- Options:
-
Resource Control
- Gated clock conversion (
-gated_clock_conversion
) - BUFG count limit (
-bufg
) - Resource sharing (
-resource_sharing
).
- Gated clock conversion (
-
Report Level (
vivado.report_level
)0
: Utilization after synthesis + timing after implementation.1
: Detailed analysis after synthesis/implementation.2
(default): Includes quick failure checks.
2. Implementation Options#
-
Implementation Strategy (
--vivado.impl.strategies
)- Predefined strategies such as performance priority (
Performance_Explore
), resource optimization (Area_Explore
), or custom strategies.
- Predefined strategies such as performance priority (
-
Number of Parallel Jobs (
--vivado.impl.jobs
)- Specify the number of parallel processes for Vivado implementation (e.g.,
--vivado.impl.jobs 4
).
- Specify the number of parallel processes for Vivado implementation (e.g.,
-
Physical Optimization (
vivado.phys_opt
)- Stage selection:
none
,place
(placement optimization),route
(routing optimization), orall
.
- Stage selection:
-
Timing Control
- Maximum number of timing paths (
vivado.max_timing_paths
): Specify the number of paths reported when timing is not met.
- Maximum number of timing paths (
-
Pblock Range (
vivado.pblock
)- Specify the logic area of interest during implementation (e.g.,
{SLICE_X8Y105:SLICE_X23Y149}
).
- Specify the logic area of interest during implementation (e.g.,
-
Resource Optimization
- The
--optimize
parameter can affect resource usage (e.g., thes
option reduces resource consumption).
- The
3. Other Key Options#
- Disable IP Cache (
--no_ip_cache
): Forces the tool to regenerate IP synthesis results. - Custom Synthesis Command (
vivado.synth_design_args
): Pass additional parameters tosynth_design
. - Physical Layout Control: Distribute implementation tasks via LSF cluster (
--vivado.impl.lsf
).
Note: Some options need to be configured through the Vitis toolchain (v++
command), while others can be adjusted through the Vivado GUI's "Project Settings" (such as synthesis strategy, implementation strategy, and number of parallel jobs). For detailed strategies, please refer to the "Vivado Design Suite User Guide".
No time to write more, just using the generated content for now.