Sawen_Blog

1 STM 32 Related Peripheral Interface Learning#

1.1 GPIO#

STM 32 F 4 Each group of general-purpose GPIO ports is controlled by 7 32-bit registers, including:

• 4 32-bit configuration registers (MODER, OTYPER, OSPEEDR, PUPDR)
• 2 32-bit data registers (IDR, ODR)
• 1 32-bit set/reset register (BSRR)
• 1 32-bit lock register (LCKR)
• 2 32-bit alternate function selection registers (AFRH, AFRL)

1.1.1 Registers#

1.1.1.1 GPIO Port Mode Register (GPIOx_MODER) (x=A.. I)#

Used to control the working mode of GPIO

Each group of GPIO has 16 IO ports, with two register bits controlling 1 IO. The reset value of PortA is 0 xA 800 0000, corresponding to the binary 1010 1000 0000 0000 0000 0000 0000 0000, indicating that PA 15/14/13 are in alternate function mode, while the other ports are in input mode.

1.1.1.2 GPIO Port Output Type Register (GPIOx_OTYPER)#

Used to control the output type of GPIO.

Does not take effect in input mode. The lower 16 bits are valid. In default output mode, the IO port is push-pull output.

1.1.1.3 GPIO Port Output Speed Register (GPIOx_OSPEEDR)#

Also only used in output mode.

1.1.1.4 GPIO Port Pull-Up/Pull-Down Register (GPIOx_PUPDR)#

• 00: No pull-up or pull-down
• 01: Pull-up
• 10: Pull-down
• 11: Reserved

1.1.1.5 GPIO Input Data Register (GPIOx_IDR)#

1.1.1.6 GPIO Output Data Register (GPIOx_ODR)#

1.1.1.7 GPIO Port Set/Reset Register (GPIOx_BSRR)#

1.2 ADC#

STM 32 F 4 has 3 independently usable ADCs, among which ADC 1 and ADC 2 can be combined into dual mode to increase the sampling rate. The ADC of STM 32 is a 12-bit successive approximation ADC. It includes 19 channels, capable of measuring 16 external and 2 internal signal sources as well as the Vbat channel signal. The A/D conversion of these channels can be performed in single, continuous, scan, and discontinuous sampling modes. The converted results are stored in a 16-bit data register of LSB or MSB.

1.2.1 Main Features#

1. Configurable 12-bit, 10-bit, 8-bit, 6-bit resolution
2. Generates interrupts at the end of conversion, end of injected conversion, analog watchdog occurrence, or overflow
3. Single and continuous conversion modes
4. Data alignment to ensure consistency of built-in data
5. Independently set sampling time for each channel
6. Discontinuous sampling mode
7. ADC power supply: 2.4 V to 3.6 V during full-speed operation, 1.8 V during slow operation
8. ADC input range: $V_{REF-} \leq V_{IN}\leq V_{REF+}$
9. Can generate DMA requests during regular channel conversion

1.2.2 Conversion Sequence#

When any ADCx multi-channel performs a series of conversions in any order, grouped conversions are born, with two types of grouped conversions: regular group and injected group. The regular group allows up to 16 input channels for conversion, while the injected group allows up to 4 input channels for conversion.

1.2.2.1 Regular Group#

Grouped conversions in a specific order, commonly used.

1.2.2.2 Injected Group#

"Injection" breaks the original state, equivalent to an interrupt. If the injected group starts during the regular group conversion, the regular group continues conversion only after the injected group conversion is completed.

1.2.2.3 Conversion Rate#

The ADC conversion time calculation formula is $$
T_{CONV}=Sample_Time+TSAR\times ADC_CLK