Error collection when generating HDL code using HDL Coder in MATLAB

Jul 14, 2025#FPGA #MATLAB18

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The document discusses errors encountered when generating HDL code using HDL Coder in MATLAB, specifically focusing on delay balancing issues. It highlights that adding input-output pipelines to modules with feedback loops can introduce extra clock delays, leading to failure in delay balancing. To resolve this, it suggests setting the input-output pipeline for feedback loop modules to zero while ensuring timing is maintained, or manually adding delays at the same-level output ports.

1 Delay balancing unsuccessful because an extra 4 cycles of latency introduced by optimizations in the feedback loop cannot be offset using design delays for the loop latency budget.#

1.1 Causes#

Due to timing considerations, 1 to 2 levels of input-output pipelining were added at the output of each module. However, adding input-output pipelining to this feedback structure results in the following error.

It can be seen that the added input-output pipelining causes additional clock delays, leading to the failure of delay balancing.

1.2 Solutions#

Set the input-output pipelining of the module with feedback loops to 0 while ensuring timing. Alternatively, a delay can be manually added to the same-level output ports to introduce pipelining.