1 DVB Standards#
Digital Video Broadcasting (DVB) is a complete digital television solution, which includes DVB-C (Digital Television Cable Transmission Standard), DVB-T (Digital Television Terrestrial Transmission Standard), and DVB-S (Digital Television Satellite Transmission Standard). This section mainly introduces the DVB-S system.
DVB-S is the digital satellite broadcasting standard, and satellite transmission has advantages such as wide coverage and large program capacity. The signal uses RS(188,204) and convolutional coding in a cascaded manner, with QPSK modulation.
2 Basic Principles of DVB-S Channel Coding and Modulation#
2.1 Principle Block Diagram#
According to the ETSI DVB-S standard, the principle block diagram is shown below:
Due to the power limitations particularly affecting DTH services provided by satellites, the main design goal should be noise and interference resistance, rather than spectral efficiency. To achieve high energy efficiency without excessively compromising spectral efficiency, the system should use QPSK modulation along with convolutional codes and RS codes in a cascaded manner.
2.2 Interface#
2.3 Channel Coding#
2.4 TS Stream Adaptation Unit#
The input TS stream is packaged according to the MPEG-2 format with a fixed length, where the packet length is 188, and the frame header is the synchronization word $47_{hex}$. The DVB-S standard requires that every 8 TS packets form a superframe, reversing the 8 synchronization headers in the superframe to become $b8_{hex}$, while the remaining synchronization headers remain unchanged. Additionally, empty packets are automatically inserted, with 16 zeros added after the data packet to extend the length of the 188-length packet to a length of 204, establishing clock matching and interface connection with the subsequent channel coding module.
2.5 Scrambling Unit#
The baseband signal contains many consecutive "1"s or "0"s, which can lead to a significant amount of low-frequency components in the baseband signal spectrum, making it unfavorable for signal transmission in the channel and for clock signal extraction at the receiver. Therefore, scrambling is used to convert the TS stream into a pseudo-random sequence. The schematic diagram of randomization in the DVB-S standard is as follows:
The generating polynomial of the pseudo-random binary sequence is as follows:
Scrambling is processed in units of superframes composed of 8 data packets. At the start of processing each unit, the sequence "100101010000000" is loaded into the register for scrambling. The synchronization word of the data packet is not scrambled.
2.6 RS Coding#
The outer code uses RS coding, which has the ability to correct both random errors and burst errors, with a more effective correction for burst errors. The coding format used in DVB-S is RS(239,255) truncated to obtain RS(188,204) coding, with a maximum correctable length of 8 bytes, and the coding starts from the synchronization word $47_{hex}$ or $b8_{hex}$.
2.7 Brief Description of the Coding Principle#
Assuming the information polynomial is
The code generating polynomial is
where a = 02_hex_, then the expansion of the generating polynomial is
After dividing $x^{16}\cdot m(x)$ by $g(x)$, the remainder is a polynomial of degree 15 in x, and its 16 coefficients are the 16 generated check bytes, which are added to the 188-length data packet to complete the RS(188,204) coding.
2.8 Convolutional Interleaving#
During digital signal transmission, some burst interference can lead to a series of data errors that may exceed the correction range of the RS code. Convolutional interleaving can disperse the erroneous characters, making the channel behave like a nearly memoryless channel. The convolutional interleaving used in DVB-S has an interleaving depth of 12. The block diagrams of interleaving and deinterleaving are as follows:
2.9 Convolutional Coding#
The inner code uses a (2,1,7) type convolutional code, with a coding efficiency of $\frac{k}{n}=\frac{1}{2}$, consisting of 6 shift registers and 2 modulo-2 adders, where 1 bit signal generates 2 bits of coded signal, with a constraint length of 7.
When the channel quality is good, redundancy can be removed from the coded signal to improve channel utilization.
3 Matlab Simulation#
3.1 TS Stream Adaptation and Scrambling Module#
3.1.1 CLKdivide#
The bitrate of a high-definition television signal is $8Mbps$, so the rate of the binary signal is $8Mbps$. The input data is of type $uint8$, so the input signal rate is $1M$. Therefore, the CLKdivide module divides the $200MHz$ clock down to $1MHz$ and $8MHz$.
3.1.2 sigSource#
This module generates the input TS stream signal and produces the start, end, and enable signals for RS coding. Since an empty packet needs to be inserted after outputting each 188-byte data packet, an enable system is used, which pulls down the enable signal after counting 188 times to insert the empty packet.
3.1.3 HeaderProcess#
This module performs rate conversion and superframe grouping on the input TS stream, combining every eight data packets into a superframe and reversing the first synchronization word from $0x47$ to $0xb8$, while generating the enable signal for sigSource. It also generates control signals for the scrambling module.
The first Multiport Switch is used for inserting empty packets, while the second Multiport Switch is used to reverse the first synchronization word of the superframe.
3.1.4 myScrambler#
Designed according to the generating polynomial of the scrambler. The enable signal generated by HeaderProcess is pulled down exactly when the input synchronization word is received, and no scrambling is performed. The reset signal for the scrambler reloads the initial sequence "100101010000000" after one superframe is input.
3.1.5 Simulation Data#
3.2 RS Coding Module#
Using modules from HDL Coder, since the clock rate is 200 $MHz$, a triggering module needs to be added to ensure that RS coding is performed at the symbol rate $R_B$.
3.3 Convolutional Interleaving#
Similarly, a triggering module is added to ensure that the interleaving speed is at the symbol rate $R_B$.
3.4 uint8 to binary Module#
First, the input data is bitwise ANDed to extract each bit of data, which is then output bit by bit using a Multiport Switch, with the enable rate of the counter being 8 times the symbol rate $R_B$.
3.5 Convolutional Coding#
Without removing redundancy, the coding efficiency is $\frac{1}{2}$. Redundancy can also be removed to achieve coding efficiencies of $\frac{2}{3}, \frac{3}{4}, \frac{5}{6}, \frac{7}{8}$. Within a certain bandwidth, the greater the coding efficiency, the greater the transmission efficiency, while the error correction capability decreases.
4 Vivado Implementation#
Most of the Vivado code is generated by HDL Coder or generated coefficient files from Matlab, which are then imported into Vivado's IP core.
4.1 DataSource_Scrambler#
When generating HDL code directly, the sigSource module in the DataSource_Scrambler module does not meet the timing requirements at a frequency of 200 $MHz$, so the following configuration is made before generating HDL:
After adding a pipeline stage at the output, the timing can pass after synthesis and routing. Additionally, a delay module is added to all output signals of this module to form a pipeline.
4.1.1 Scrambling Module#
It can be seen that after every 8 data packets are input, the initial value of the internal D flip-flops in the scrambler is reset, while the reversed synchronization word $0xb8$ is not scrambled.
4.1.2 Data Alignment#
During simulation, it was found that the synchronization word $0xb8$ and the enable signal for RS coding were not aligned, so the following module was added:
By delaying the output enable signal by one data cycle, the synchronization of the signals can be ensured.
4.2 RS Coding#
The data from ModelSim is imported into Matlab for decoding, and it can be seen that all 188 data packets have been completely decoded.
4.3 Raised Cosine Roll-off Filter#
4.3.1 Matlab Filter Design#
According to the requirements of the DVB-S standard, the raised cosine roll-off factor is $0.35$, and the filter coefficients are designed using Matlab's filterDesigner tool.
In the FPGA, the filter coefficients need to be fixed-point processed.
After quantizing the coefficients to 32 bits, the amplitude response is as follows:
After quantizing the coefficients to 16 bits, the amplitude response is as follows:
It can be seen that the amplitude response of the 16-bit quantization is almost the same as that of the 32-bit quantization. To save space, 16-bit quantization is used.
After quantization, click on Target → Xilinx Coefficient File to generate the .coe file.
4.3.2 Vivado FIR Filter Design#
Select Source as COE File.
The input sampling frequency must match the clock frequency, without oversampling.
In Implementation, select the coefficient type as signed, and set the bit width to 16.
The input signal is ±1, so the input bit width is 2, with the first bit as the sign bit. The output mode is set to full precision.
4.3.3 Waveform#
5 Using XDMA for Data Input and Output Acquisition#
The structural block diagram is shown above.
The overall structure of the project is shown above, where data is written into the system through the XDMA M_AXIS_H2C interface. Since the width of the written data is 128 bits and the input width of the signal processing part in the project is 8 bits, an AXISDataWidthConverter module is added to convert the width from 16 BYTE to 1 BYTE and write it into FIFO. The AXIGPIO module reads the FIFO's almost full signal; if the FIFO is full, the almost full signal is pulled high, stopping data writing. When reading the QPSK signal generated by DVB-S, the signal width has already increased due to raised cosine roll-off filtering and modulation, so to reduce complexity, the modulated signal is zero-padded to 128 bits before being output to the Host through the M_AXIS_C2H interface.
The debugging process can be seen at