With the development of chip technology, the sampling rate of ADCs is becoming increasingly high, leading to digitalization getting closer to the system front end. Currently, the commonly used technique in engineering is intermediate frequency sampling, which digitizes the analog signal at intermediate frequency. At this point, the sampling rate of the ADC is below the minimum sampling rate dictated by the Nyquist sampling theorem (twice the signal bandwidth), resulting in oversampling. Oversampling can evenly distribute the inherent quantization noise of the sampling process over a larger bandwidth, reducing the noise power on the target signal bandwidth, and subsequently filtering out the out-of-band noise through a filter, thus producing a better signal-to-noise ratio than critically sampled signals.
When the signal is sampled by the ADC and transmitted to the FPGA, the signal enters the digital domain. However, excessively high sampling rates can put significant pressure on subsequent signal processing. To alleviate this pressure, it is necessary to reduce the sampling rate of the signal, which is called decimation. The data rate of the decimated signal is relatively low, effectively reducing the occupancy of FPGA resources and helping to simplify the timing convergence of the system.
When driving high-speed DACs, it is necessary to increase the sampling rate of the signal, which is called interpolation. The higher the sampling rate of the DAC, the greater the frequency domain separation of the output spectrum, which can simplify the operation of the analog filter after the DAC, thereby improving the signal-to-noise ratio.
A typical application of multi-rate signal processing is digital up conversion (DUC) and digital down conversion (DDC).