FIFO is essentially a first-in, first-out data buffer composed of RAM and read/write logic. The difference from RAM is that FIFO does not have external read/write address lines; it writes data in sequence and reads it in the same order. The data address is incremented by internal read/write pointers, so there is no need to consider read/write conflicts during operations.
According to the clock domain in which FIFO operates, it can be divided into synchronous FIFO and asynchronous FIFO. The read clock and write clock of synchronous FIFO are the same, commonly used for temporary buffering where the data bit widths on both sides differ. Asynchronous FIFO has inconsistent read and write clocks, often used for processing data signals across clock domains.
Timing Diagram#
Synchronous FIFO#
In the initial state, the empty signal is high, indicating that the FIFO is empty. If a read operation is initiated at this time, the data read will be invalid. When wr_en is pulled high, data begins to be written into the FIFO. Once there is data in the FIFO, the empty signal will go low. After initiating read and write operations simultaneously, the flag will not change since it is a synchronous FIFO.
When writing without reading, if there are two or more data items in the FIFO, the almost empty signal will also go low. When the FIFO is full, and it can only accept one write operation without reading, the almost full signal will go high. Finally, if a write operation is performed without any read operation, the full signal will go high, indicating that the FIFO is now full. No further data can be written until a read request is made; if data is written at this point, it will be lost.
AXIS FIFO#
The timing diagram is as follows:
When writing data, s_axis_tvalid is high, and full is low, which means s_axis_tready is high, allowing data to be written.
Similarly, for reading data, data can only be read when both valid and ready signals are high. m_axis_tvalid corresponds to the wr_en signal of the FIFO, m_axis_tready corresponds to the inverted full signal of the FIFO, s_axis_tvalid corresponds to the inverted empty signal of the FIFO, and s_axis_tready corresponds to the rd_en of the FIFO.
AXIS FIFO#
The IP core interface of Axis FIFO is as follows:
This time, we are learning about asynchronous read and write of FIFO, so independent clock is selected as 'Yes', and packet mode is not enabled. The Bd block diagram is as follows:
The clk_wiz output has two ports, with port 1 having a clock rate of $100MHz$ and port 2 having a clock rate of $50MHz$. The source code for axis_data_source and axis_dest is as follows:
module axis_data_source (
input s_axis_clk,
input s_axis_rstn,
input m_axis_tready,
output [7:0] m_axis_tdata,
output m_axis_tvalid
);
reg [7:0] cnt;
always @(posedge s_axis_clk or negedge s_axis_rstn) begin
if(!s_axis_rstn) begin
cnt<=0;
end
else begin
if(m_axis_tready) begin
if(cnt==255) begin
cnt<=0;
end
else begin
cnt<=cnt+1'b1;
end
end
end
end
assign m_axis_tdata=cnt;
assign m_axis_tvalid=1'b1;
endmodule
/*read fifo data*/
module axis_dest (
input s_axis_clk,
input s_axis_tvalid,
input [7:0] s_axis_tdata,
output s_axis_tready
);
assign s_axis_tready=1'b1;
endmodule
The data_source generates and outputs $0-0xFF$ at a rate of $100MHz$, while axis_dest continuously reads data at a rate of $50MHz$. The timing diagram is as follows:
At the beginning, the FIFO is not full, and writing and reading do not interfere with each other. As data continues to be written and cannot be read immediately, after a period, the FIFO's full signal goes high, corresponding to the m_axis_tready signal going low, and axis_data_source stops generating new data. The simulation diagram is as follows:
At this point, the rates of writing and reading are synchronized through the valid and ready signals.