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2023 National Competition C Problem "Capacitor and Inductor Measurement Device" Design Report

1 Measurement Principle#

Refer to the solution on the following website

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Referring to the LCR tester, the basic working principle is to apply a sine excitation signal to the DUT, and then measure the voltage across the DUT and the current flowing through the DUT, from which the properties and parameters of the DUT can be calculated.

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For an ideal capacitor, the current phase should lead the voltage across the capacitor by 90°. However, real capacitors have losses, which can be equivalently represented as a parallel combination of an ideal capacitor $C_p$ and an ideal resistor $R_p$. Therefore, the phase of the current leading the voltage will be less than 90°, and this phase difference is the loss angle.

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Assuming the voltage across the DUT is $\dot{V}=V\cos(\omega t)$, the current flowing through the DUT is $\dot{I}=I \sin(\omega t - \varphi)$, the projection of the current on the imaginary axis is the current flowing through the ideal capacitor, and the projection on the real axis is the current flowing through the resistive loss.

Thus, the capacitive reactance of the parallel capacitor can be calculated as $X_{Cp}=\frac{V}{I \cos\varphi}$, and the capacitance value $C_P=\frac{1}{\omega X_{Cp}}=\frac{I \cos \varphi}{\omega V}$.

The value of the resistive loss is $R_p=\frac{V}{I \sin\varphi}$.

The ratio of the reactive power consumed by the component to the active power is defined as the Q value of the component, and the reciprocal of the Q value is the D value (tangent of the loss angle)

Q=RPXCp=cotφ,D=1Q=tanφQ=\frac{R_P}{X_{Cp}}=\cot \varphi, D=\frac{1}{Q}=\tan \varphi

The required parameters above can be obtained using orthogonal algorithms:

Isin(ωtφ)Vcos(ωt)=12VIsin(2ωtφ)12VIsinφIsin(ωtφ)Vsin(ωt)=12VIcos(2ωtφ)+12VIcosφ \begin{align}I\sin(\omega t-\varphi)\cdot V\cos(\omega t) & = \frac12VI\sin(2\omega t-\varphi)-\frac12VI\sin\varphi\\I\sin(\omega t-\varphi)\cdot V\sin(\omega t) & = -\frac12VI\cos(2\omega t-\varphi)+\frac12VI\cos\varphi \end{align}

After multiplication and passing through a low-pass filter, the DC components $-\frac{1}{2} VI \sin\varphi$ and $\frac{1}{2} VI \cos\varphi$ can be obtained, allowing us to determine the required tangent of the loss angle

tanφ=VIsinφVIcosφ\tan\varphi = \frac{VI \sin \varphi}{VI \cos \varphi}

At the same time, the following parameters can be obtained

The capacitive reactance of the ideal capacitor in parallel Xcp=VIcosφ=V2VIcosφ, capacitance is Cp=1ωXcp, the resistive loss in parallel Rp=VIsinφ=V2VIsinφ. Where V2 can be obtained by squaring the voltage and filtering out high-frequency components.\text{The capacitive reactance of the ideal capacitor in parallel }X_{cp}=\frac{V}{I\cos\varphi}=\frac{V^2}{VI\cos\varphi} \text{, capacitance is }C_p=\frac{1}{\omega X_{cp}}, \text{ the resistive loss in parallel }\\R_{p}=\frac{V}{I\sin\varphi}=\frac{V^2}{VI\sin\varphi}\text{. Where }V^2\text{ can be obtained by squaring the voltage and filtering out high-frequency components.}

2 Parameter Simulation#

The existing ADC input voltage range is 0~2V, with an input bias of 1V; the DAC output voltage range is 1V peak-to-peak, and a bias can also be added,

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When the capacitance value is 1nF-100nF and the shunt resistor is 0.33Ω, the output voltage peak-to-peak is 4-200mV. When measuring inductance at a frequency of 1MHz, with inductance values of 10uF-100uF, the output voltage peak-to-peak is 15-150mV. Since the ADC module's input range is 0~2V, the signal is amplified by 9 times, increasing the peak-to-peak value to about 1.8V.

2.1 Debugging Records#

The signal output from the DAC does not match the impedance of the LC filter, resulting in a low amplitude of the signal at the input of the LC filter.

After powering on the detection circuit for the DUT, there is a -500mV bias at the input.

The LC filter is designed as follows; when the DAC outputs a 1MHz signal, the higher harmonics are quite severe, so an LC low-pass filter with a passband of 1.2MHz is designed to filter out high-frequency noise.

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3 PCB Design#

3.1 Initial Version#

R8 is used to connect the test fixture, with the excitation signal input from P1, passing through the DUT capacitor or inductor on R8, and the current flowing into the subsequent current detection circuit through C5.

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With this design, the input impedance of the circuit is the impedance value of the DUT at a specific frequency, while the output impedance of the front amplifier is 50Ω, which causes the amplitude of the input signal to not be the expected value.

3.2 Improvement#

Remove the 50Ω resistor used for impedance matching at the output of the front amplifier, utilizing the low output impedance characteristic of the operational amplifier to ensure that all the output signal voltage is applied to the input of the above circuit.

The reason for this improvement is that if the operational amplifier's output stage does not drive a capacitive load, the LC filter, and long coaxial cables, the output does not need to connect to a matching resistor.

4 FPGA Program Design#

Based on the above principles, two ADCs are needed to collect current and voltage signals, and one DAC to generate the excitation signal. Therefore, the DE0nano is chosen, which has two extended 40-pin headers that can connect to two ADDA modules.

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The FPGA's crystal oscillator frequency is 50MHz, and through PLL division, 20MHz and 80MHz are generated, where the ADC clock is 20M and the DAC clock is 80M. They are then connected to ADC_Interface and DAC_Interface respectively.

The width of the signal collected by the ADC is 10 bits, discarding the lowest two bits for subsequent signal processing. After collecting 1024 samples, it pauses for 0.5 seconds before the next collection.

The DAC section uses an NCO to generate a sine wave signal, switching the frequency word via a dip switch, outputting to DAC_interface, left-shifting by 1 bit before outputting, and then amplifying by 2 times through a non-inverting amplifier to enhance the signal's driving capability.

The current and voltage data collected by the ADC are stored in RAM, and phase shifting is achieved by changing the starting address for reading. The ADC's sampling rate is 20M, and when collecting 100K signals, 200 points are collected per cycle. Therefore, to achieve a phase shift of $\frac{\pi}{2}$, it is only necessary to start reading data from 50 in RAM, and the read signal will be the signal read from RAM starting from 0, phase-shifted by $\frac{\pi}{2}$.

The data collected by the ADC is unsigned, and performing multiplication filtering will not match the calculation results. Therefore, an additional module to convert unsigned to signed numbers is added, converting to signed numbers before multiplication, and then sending it through a low-pass filter to obtain the required values. The output of the low-pass filter is truncated, keeping only the high 16 bits of the data to reduce the impact of jitter in the DC signal on the results.

5 Measurement Results#

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The output of the first Lowpass is $VI\cos\phi$, the output of the second Lowpass is $\frac{1}{2}VI\cos \varphi$, and the output of the third Lowpass is $V^2$. The calculation process for the capacitive reactance is as follows:

Based on the fitting relationship between the simulated input current and output voltage, it can be obtained that the amplitude of the output collected voltage equals the current ÷ 0.305, thus the capacitive reactance is the third output ÷ 2 ÷ the first output ÷ 0.305.

5.1 Circuit Display#

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6 Future Plans#

Add SPI communication to transfer the sampled calculated data to the TI development board for further computation and display.

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